Macrostructure Logic Arrays. Volume 4. Task 4, 5, 6 and 7: Software Development and GN&C Processor Development
Abstract
The primary objective of this research effort is to develop the technology necessary to construct a light weight, low power, high performance flight computer for guidance, navigation, and control of advanced kinetic energy weapon interceptors. The mission of the flight computer is to guide the interceptor to a point in space during the boost phase, receive update information and orient the interceptor to a designated target space during midcourse, track the targets and perform necessary maneuvers and divert operations to guide the interceptor into an incoming RV (reentry vehicle) at the terminal phase. The bulk of the processing power is required in the terminal phase. During this phase, the flight computer must process images from a 128x128 focal plane array (FPA), perform various types of filtering operations on the images, and convert the images into object clusters for tracking. The basic required interfaces for the GN&C processor are to the Inertial Measurement Unit and the valves that control the various thrusters in the interceptors. This basic interface requires relatively low communication bandwidth with the GN&C processor. (kr)
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 07, 1990
- Accession Number
- ADA228565
Entities
People
- Andy Register
- Joseph Chamdani
- Randy Abler
- Sam Russ
- Wei S. Tan
Organizations
- Georgia Tech