Microsupercomputers: Design and Implementation
Abstract
1. Executive Summary. A summary of progress for the period April 1989 through October 1989 follows: (1) Parallel Architecture: The Stanford DASH multiprocessor advances the state of parallel computing by combining the programmability of shared-memory machines with the scalability of distributed-memory machines. (2) Parallel Software: We have developed a compiler algorithm that applies a large set of loop-level optimizations to improve data locality in programs. (3) Super-Scalar Design: We have investigated how much parallelism is available at the lowest level -- in the base instruction stream of a processor. (4) Multi-level Caches: The presence of a second-level cache can decrease the optimum size and cycle time of the first-level cache, and significantly improve performance beyond the best attainable with a single level of caching. (5) Testers: A single chip tester, called Testarossa, contains a dRAM for the test vector storage, a decompressor to increase the effective vector size, and the pin electronics for 16 DUT pins. (6) Computer Aided Design: In the area of algorithm and tool development for high-level synthesis we have targeted two goals: control generation for synthesized structures and relative scheduling techniques under timing constraints. (7) Simulation: The goal of this research is to provide application tools for the proposed scalable shared memory multiprocessor.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 01, 1989
- Accession Number
- ADA228743
Entities
People
- John L. Hennessy
- Mark A. Horowitz
Organizations
- Stanford University