Application of Error Correcting Codes in Fault-Tolerant Logic Design for VLSI Circuits
Abstract
It is now generally accepted that not all faults in VLSI logic can be represented by the stuck-at-0 and stuck-at-1 models used at the gate level. In order to ensure realistic modeling, faults should be considered at the transistor level, since only at the level the complete circuit structure is known. In other words, test for circuits should be derived based on possible 'shorts' and 'opens' at the transistor level. A stuck-open or stuck-closed transistor can be modeled by replacing the faulty transistor with an open connection or a direct short respectively between the transistor's source and drain. (rh)
Document Details
- Document Type
- Technical Report
- Publication Date
- May 31, 1990
- Accession Number
- ADA228840
Entities
People
- H. L. Martin
- P. K. Lala
Organizations
- North Carolina Agricultural and Technical State University