A Generalized Extraction System for VLSI

Abstract

A Generalized Extraction System for VLSI (GES< pronounced guess) is described. GES, which is written in Prolog, performs logic extraction from transistor netlists, identification of logic errors within and between components, and generation of VHDL. The input to GES consists of a transistor netlist using format from extract in magic. Logic extraction has been performed, on transistor netlists extracted from design layouts in magic, up to the level of 32-bit adders and 32-bit registers. GES reports typical errors in the construction and interconnection of components. An error-report identifies the component and specifies its location within the magic layout, making it easy to locate the offending circuitry. GES also provides a hierarchical VHDL description of the layout-design that is verified to be free of a large class of design errors. (RH)

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 1990
Accession Number
ADA230396

Entities

People

  • Frank Markham
  • Joanne E. Degroat
  • Michael A. Dukes

Organizations

  • Wright Laboratory

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Fields of Study

  • Physics

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