Test Generation for Digital Circuits Using Parallel Processing

Abstract

The problem of test generation for digital logic circuits is an NP-Hard problem. Recently, the availability of low cost, high performance parallel machines has spurred interest in developing fast parallel algorithms for computer-aided design and test. This report describes a method of applying a 15-valued logic system for digital logic circuit test vector generation in a parallel programming environment. A concept called fault site testing allows for test generation, in parallel, that targets more than one fault at a given location. The multi-valued logic system allows results obtained by distinct processors and/or processes to be merged by means of simple set intersections. A machine-independent description is given for the proposed algorithm.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1990
Accession Number
ADA231006

Entities

People

  • Akhtar-uz-zaman M. Ali
  • Carlos R. Hartmann

Organizations

  • Syracuse University

Tags

DTIC Thesaurus Topics

  • Abstracts
  • Circuits
  • Computations
  • Computer Programming
  • Computer-Aided Design
  • Computers
  • Construction
  • Digital Circuits
  • Inversion
  • Lists (Data Structures)
  • Logic
  • Logic Gates
  • Parallel Computing
  • Parallel Processing
  • Parallel Processors
  • Xor Gates

Fields of Study

  • Computer science

Readers

  • Computer Science.
  • Graph Algorithms and Convex Optimization.
  • Systems Analysis and Design