VHSIC Hardware Description Language (VHDL) Benchmark Suite

Abstract

This report documents changes and additions made to the VHDL benchmark Suite released in October 1989 (WRDC-TR-89-5046). Each benchmark is designed to test one or more of a set of 71 VHDL language features in terms of the limitations of user's or vendor's system architecture, operating system, and VHDL toolset. These limitations could include CPU time and amount of memory required to simulated a test. Examples of language feature tests are the maximum number of signal declarations allowed in an architecture or the maximum size (number of characters) of a process label.

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 1990
Accession Number
ADA231276

Entities

People

  • Karen M. Serafino
  • Michael A. Dukes

Organizations

  • Wright Laboratory

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Air Force
  • Classification
  • Computer Programs
  • Computers
  • Directories
  • Environment
  • Generators
  • Hierarchies
  • Language
  • Operating Systems
  • Personality
  • Recursive Functions
  • Simulations
  • Simulators
  • Standards
  • Waveforms

Fields of Study

  • Computer science
  • Engineering

Readers

  • Database Systems and Applications
  • Parallel and Distributed Computing.