Design of a Pipelined Multiplier Using a Silicon Compiler

Abstract

This thesis describes the design methodology and the process of employing the GENESIL Silicon Compiler (GSC)(Version 7.1) in the layout of a pipelined multiplier, in 1.5 micron CMOS technology, using a parallel multiplier cell array. Additionally, background material on the theory of multiplication, as well as the concept and theory of pipelining are presented. The results revealed two practical limits of the GSC system which precluded achieving the high component density made possible by full custom manual CAD methods using graphic layout tools. Although the GSC system did not perform as desired in this study, it offers a viable alternative to the labor intensive, full custom, Very Large Scale Integration graphic layout tools in use today.

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1990
Accession Number
ADA236679

Entities

People

  • Ronald S. Huber

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Abstracts
  • Circuits
  • Compilers
  • Complementary Metal-Oxide Semiconductors
  • Computers
  • Digital Signal Processing
  • Electrical Engineering
  • Fabrication
  • Integrated Circuits
  • Materials
  • Metal Oxide Semiconductors
  • Operating Systems
  • Semiconductors
  • Signal Processing
  • Simulations
  • Systems Engineering
  • Very Large Scale Integration

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.
  • Systems Analysis and Design