Asynchronous Design for Parallel Processing Architectures

Abstract

The objective of this research is to provide an interconnect synthesis methodology which facilitates a modular design approach without compromising the global performance. The main tasks of this effort will be the development of the theory for optimal interconnect circuit synthesis from a high level specification, with emphasis on testability and fault tolerance asynchronous interface among concurrently computing hardware, and the application of this design methodology to physical implementations of parallel processing systems.

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Document Details

Document Type
Technical Report
Publication Date
Jul 01, 1991
Accession Number
ADA237696

Entities

People

  • Teresa H. Meng

Organizations

  • Stanford University

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algorithms
  • Automation
  • Circuits
  • Computer-Aided Design
  • Electronic Mail
  • Fault Tolerance
  • Integrated Circuits
  • Parallel Computing
  • Parallel Processing
  • Specifications
  • Standards
  • Transitions
  • Workshops

Readers

  • Parallel and Distributed Computing.
  • Software Engineering