A Parallel Rendering Algorithm for MIMD Architectures

Abstract

Applications such as animation and scientific visualization demand high performance rendering of complex three dimensional scenes. To deliver the necessary rendering rates, highly parallel hardware architectures are required. The challenge is then to design algorithms and software which effectively use the hardware parallelism. This paper describes a rendering algorithm targeted to distributed memory MIMD architectures. For maximum performance, the algorithm exploits both object level and pixel level parallelism. The behavior of the algorithm is examined both analytically and experimentally. Its performance for large numbers of processors is found to be limited primarily by communication overheads. An experimental implementation for the Intel iPSC/860 shows increasing performance from 1 to 128 processors across a wide range of scene complexities. It is shown that minimal modifications to the algorithm will adapt it for use on shared memory architectures as well.

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1991
Accession Number
ADA237743

Entities

People

  • Thomas W. Crockett
  • Tobias Orloff

Tags

Communities of Interest

  • Air Platforms
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Algorithms
  • Boundaries
  • Computations
  • Computers
  • Contracts
  • Data Transmission
  • Databases
  • Engineering
  • Equations
  • Floating Point Operations
  • Graphics
  • Parallel Computing
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Fields of Study

  • Computer science
  • Engineering

Readers

  • Computer Vision.
  • Parallel and Distributed Computing.