High Speed Systolic Array Processor (HiSSAP) System Development Synopsis: Lesson Learned.

Abstract

This report documents the design rationale of the High Speed Systolic Array Processor (HiSSAP) testbed. In addition to reviewing general parallel processing topics, the impact of the HiSSAP testbed architecture on the top level design of the diagnostic and software mapping tools is described. Based on the experience gained in the mapping of matrix-based algorithms on the testbed hardware, specific recommendations are presented in the form of lessons learned, which are intended to offer guidance in the development of future Navy signal processing systems.

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Document Details

Document Type
Technical Report
Publication Date
May 01, 1991
Accession Number
ADA239197

Entities

People

  • J. P. Loughlin

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algorithms
  • Application Software
  • Central Processing Units
  • Communication Channels
  • Computer Programming
  • Computers
  • Data Transmission
  • Debugging
  • Digital Communications
  • Direction Finding
  • Lessons Learned
  • Parallel Computing
  • Parallel Processing
  • Parallel Processors
  • Signal Processing
  • Software Development
  • Software Development Tools

Fields of Study

  • Computer science

Readers

  • Military Logistics and Supply Chain Management
  • Radar Systems Engineering.
  • Software Engineering.