Shallow-Buried-Channel CCDs with Built-In Drift Fields
Abstract
The performance of charge-coupled devices (CCDs) is limited by the charge that is left behind after the bulk of the charge packet has transferred by Coulomb repulsion. In the absence of drift fields these residual electrons will transfer by thermal diffusion, which is a very slow process. The CCD speed can be enhanced by designing structures with strong fringing fields between gates, such as deep-buried-channel CCDs. Deep-buried-channel delay lines have indeed been demonstrated at record speeds (hundreds of megahertz), but they have several disadvantages that may ultimately limit their usefulness. For example, the shape of the potential wells is distorted, degrading linearity and affecting the overall signal-processing performance of the CCD. Furthermore, the charge- handling capacity decreases as the channel moves into the bulk, and at least 10- V clocks are required. These 10-V clocks are not only difficult to generate at high speed, but are incompatible with the 5-V technology necessary for the high- performance on-chip support circuits that interface with the CCD. To overcome these disadvantages a technique was developed to improve the charge-transfer efficiency (CTE) in buried-channel CCDs while maintaining low clock voltages and large charge capacity. Shallow-buried-channel delay lines with a channel depth of 300 nm were designed, fabricated, and tested. These delay lines operate with 5-V two-phase clocks and have a built-in potential gradient to improve the CTE.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 12, 1991
- Accession Number
- ADA240744
Entities
People
- A. L. Lattes
- S. C. Munroe
Organizations
- Massachusetts Institute of Technology