Embedded Fault-Tolerant Computer for Mission Critical Applications
Abstract
The objective of this effort is to develop an Embedded Fault-Tolerant Computer (EFTC) using a combination of off the shelf and custom hardware and software components. This prototype will then be analyzed in order to determine the concept feasibility. This report summarizes the main activities and results of the EFTC development as it has progressed through Phase II. It describes: the development of the EFTC system from evolution through hardware and software design (Section 2); brassboard implementation of hardware and software (Section 3); and the successful demonstration of generic capabilities as well as applications (Section 4). In addition, summaries of various ways in which the system can be enhanced illustrate the flexibility of the design (Section 5).
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 01, 1991
- Accession Number
- ADA242886
Entities
People
- Gary A. Kravetz