Northwest Laboratory for Integrated Systems, University of Washington, Semiannual Technical Report Number 1, July 1-November 8, 1991

Abstract

Contents: (1) Retiming of Level-Clocked Circuits; (2) Triptych - A new Field-Programmable Gate Array Architecture; (3) Subgraph Isomorphism; (4) Symbolic Timing Verification and High Level Synthesis; (5) Synthesis of Microcontroller-Based Embedded Systems; (6) Chaos Router; and (7) The MacTester.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Nov 08, 1991
Accession Number
ADA243028

Entities

People

  • Carl Ebeling
  • Gaetano Borriello
  • Lawrence H Snyder

Organizations

  • University of Washington

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Clocks
  • Communication Channels
  • Computer Programming
  • Computer Programs
  • Computer Science
  • Computers
  • Corporations
  • Digital Signal Processing
  • Embedded Systems
  • Field Programmable Gate Arrays
  • Integrated Circuits
  • Integrated Systems
  • Language
  • Logic Gates
  • Scheduling (Production)
  • Signal Processing
  • Two Dimensional

Readers

  • Graph Algorithms and Convex Optimization.
  • Integrated Circuit Design and Technology.
  • Technical Research and Report Writing.