Fault Tolerant Architectures for Multiprocessors and VLSI-Based Systems

Abstract

A general framework for shift register-based test response compressors was developed based on algebraic coding theory. It has advantages over Markov modeling in allowing exact computation of aliasing probability and extension to other forms of built-in self-test. The use of deBruijn graphs was adopted to studies of VLSI-based multiprocessor networks. These allowed derivation of lower bounds on VLSI layout areas and provided a method to meet those bounds. The graphs were extended to hyper-de Bruijn networks. Finally a design was produced for fault-tolerant testable RAM's (TRAM's).

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Sep 29, 1991
Accession Number
ADA244034

Entities

People

  • Dhiraj K. Pradhan

Organizations

  • University of Massachusetts Amherst

Tags

Communities of Interest

  • Engineered Resilient Systems
  • Space

DTIC Thesaurus Topics

  • Algorithms
  • Computations
  • Computer Science
  • Computers
  • Computing System Architectures
  • Electrical Engineering
  • Engineering
  • Fabrication
  • Failure Mode And Effect Analysis
  • Fault Tolerance
  • Fault Tolerant Computing
  • Information Science
  • Markov Models
  • Network Architecture
  • Parallel Computing
  • Parallel Processing
  • Probability

Fields of Study

  • Engineering

Readers

  • Computer Networking
  • Graph Algorithms and Convex Optimization.
  • Software Engineering