Requirements Analysis for a Hardware, Discrete-Event, Simulation Engine Accelerator.

Abstract

An analysis of a general Discrete Event Simulation (DES), executing on the distributed architecture of an eight mode Intel PSC/2 hypercube, was performed. The most time consuming portions of the general DES algorithm were determined to be the functions associated with message passing of required simulation data between processing nodes of the hypercube architecture. A behavioral description, using the IEEE standard VHSIC Hardware Description and Design Language (VHDL), for a general DES hardware accelerator is presented. The behavioral description specifies the operational requirements for a DES coprocessor to augment the hypercube's execution of DES simulations. The DES coprocessor design implements the functions necessary to perform distributed discrete event simulations using a conservative time synchronization protocol.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1991
Accession Number
ADA244202

Entities

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  • Paul J. Taylor Jr.

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  • Air Force Institute of Technology

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  • Materials and Manufacturing Processes

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  • Air Force
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  • Content Addressable Memory
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  • Department Of Defense
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  • Engineering

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