A Design of Floating Point FFT Using Genesil Silicon Compiler

Abstract

The hardware of floating-point MULTIPLY, ADD, and SUBTRACT units are designed to support the multiplication, addition, and subtraction operation necessary in the Fast Fourier Transform (FFT). In this thesis, the IEEE floating-point standard is adopted and scaled down to 16 bits, but the exponent is an excess-8 number represented using radix-2. A 16 bit reduced word size floating-point arithematic unit for high speed signal analysis was implemented. The layout verification, functional simulation, and timing analysis of these units have been performed on the Genesil Silicon Compiler (GSC) system that was developed to overcome the shortcomings of the time consuming custom layout methods. The design of this thesis work can be used for further investigation of the high speed, pipelined floating-point arithmetic units.

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1991
Accession Number
ADA245149

Entities

People

  • Chung-kuei Lu

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Advanced Electronics
  • Biomedical
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Arithmetic
  • Arithmetic Units
  • Compilers
  • Computers
  • Converters
  • Engineering
  • Fast Fourier Transforms
  • Floating Point Operations
  • Frequency Domain
  • Lepidoptera
  • Signal Processing
  • Simulations
  • Simulators
  • Standards
  • Systems Engineering
  • Verification
  • Very Large Scale Integration

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.
  • Regression Analysis.