Minimization of Multiple-Valued Programmable Logic Array Using Simulated Annealing

Abstract

Guaranteed minimal realizations of multi-valued programmable logic arrays can only be accomplished by an exhaustive search. Exhaustive search is not very realistic for complex expressions due to the immense amount of Central Processing Unit time required to reach a solution. To circumvent this problem, heuristics have been developed. They provide near-minimal solutions, but use substantially less CPU time. This thesis investigates a new type of heuristic which is built on the foundation of simple implicant operations controlled by an annealing process. This new type of heuristic is superior to existing heuristics with respect to minimization capability but requires more CPU time.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1991
Accession Number
ADA245173

Entities

People

  • Robert C. Earle

Organizations

  • Naval Postgraduate School

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  • Central Processing Units
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  • United States Naval Academy

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