Complementary Metal Oxide Silicon Cyclic Redundancy Check Generators
Abstract
This thesis introduces an economical way of implementing the test pattern generation for built-in test. A layout generator as well as a netlist generator are written and validated. In addition, we use the netlist generator to investigate the properties of nonprimitive polynomials. When a logic chip or board has been fabricated, testing is performed on the finished product to ensure that it is free of manufacturing defects. The device is mounted in the test socket of the tester which drives its input terminals with logic signals called test vectors. The responses to these input stimuli are then obtained at the output terminals of the device. The test patterns are generated either by a software algorithm or by hardware built into the test equipment or by hardware actually embedded in the device to be tested. Good responses are obtained by stimulation or by measurement of the output of a number of 'good' devices. Responses to the test patterns may be compressed into a unique binary number which accumulates all the response data.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 1991
- Accession Number
- ADA246140
Entities
People
- Miao Chin
Organizations
- Naval Postgraduate School