Implementation of Residue Code as a Design for Testability Strategy Using Genesil Silicon Compiler

Abstract

This thesis describes the need for including design for testability in a VLSI chip design and provides information on implementing a DFT strategy using the GENESIL Silicon compiler. Two structured techniques of design for testability, Scan Design and Built-in Self Test, are discussed. Also, the methodology used to implement the residue code with GENESIL for testing the multiply-add module of a second-order Infinite Impulse Response notch filter is presented. The cost, in terms of increased hardware and decreased performance, associated with implementing the residue code is examined by comparing modulo-3 and modulo-15 checking algorithms.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1990
Accession Number
ADA246425

Entities

People

  • John E. Lawson

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Algorithms
  • Application-Specific Integrated Circuits
  • Computers
  • Digital Information
  • Electrical Engineering
  • Engineering
  • Fabrication
  • Integrated Circuits
  • Logic Gates
  • Notch Filters
  • Semiconductors
  • Simulations
  • Test And Evaluation
  • Test Equipment
  • Test Methods
  • Very Large Scale Integration
  • Xor Gates

Readers

  • Computer Programming and Software Development.
  • Integrated Circuit Design and Technology.
  • Phased Array Antenna Design.