An Analysis of Aliasing in Built-In Self Test Procedure

Abstract

This thesis investigates aliasing probability in Built-in Self Test (BIST) procedure, in which a Linear Feedback Shift Register (LFSR) is used as pseudo-random pattern generator, with a full adder as Circuit Under Test (CUT). The Signature Analyzer implements a Multiple Input Signature Register (MISR) as a test response compressor.

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1991
Accession Number
ADA246905

Entities

People

  • Jasa Barus

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Advanced Electronics
  • C4I
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Analyzers
  • Circuit Analysis
  • Circuit Testers
  • Circuits
  • Complementary Metal-Oxide Semiconductors
  • Compressors
  • Computer Programs
  • Computers
  • Digital Circuits
  • Engineering
  • Failure Mode And Effect Analysis
  • Indonesia
  • Integrated Circuits
  • Logic
  • Manufacturing
  • Markov Processes
  • Test Equipment

Readers

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