Smart BIT/TSMD Integration
Abstract
The problem of false alarms and intermittent failures of electronics continually manifest themselves in high levels of Cannot Duplicate (CND) and Retest OK (RETOK) reports. These conditions lead to an excessive drain on resources including spares, manpower and test equipment and ultimately produce a negative impact on mission readiness. A major contributor of false alarms/ intermittents is that of external environmental factors. Smart Built-in Test (Smart BIT) uses environmental stress data as inputs to its artificial intelligence based reasoning process for detecting false alarms, and Time Stress Measurement Device (TSMD) technology provides a capability to measure, collect and store stress data for failure correlation, although with minimal attention to date to real-time applications Until now, these technologies were independent research and development activities. This report discusses the integration of these technologies. A self contained laboratory testbed was developed to support this research. Hardware and software computer design and development necessary to investigate and complete the integration are detailed. Methods for simulating the environment based on real world data as well as actual sensor hardware implementations were developed. Guidelines for installing actual electronics in the testbed are provided along with conclusions and recommendations for fielding an integrated capability.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1991
- Accession Number
- ADA247192
Entities
People
- Charles Cooper
- Kenneth A. Haller
- Paul Skeberdis
- Victor G. Zourides
- White Gibson
Organizations
- Grumman