Experimental Evaluation of Incorporating Digital and Analog Integrated Circuit Die on a Common Substrate Utilizing Silicon-Hybrid Wafer-Scale Integration Technology
Abstract
The objective of this research effort was to investigate the implementation of analog circuits in a wafer scale integration system. A test circuit composed of analog and digital subsystems was designed and tested through simulation. IC die containing this test circuit were utilized in the WSI system fabrication. Preliminary investigations were conducted to evaluate the potential improvements to the IC die mounting procedure, a key step in fabricating functional WSI systems. These investigations demonstrated a procedure which produced repeatable results in achieving acceptable planarization of IC die and host substrate surfaces. These investigations also demonstrated the successful application of a barrier coating material to prevent adhesion between the IC die adhesive and reference flat during the IC die mounting procedure. An evaluation of candidate polyimides to be used as the interlevel dielectric in the WSI systems was also performed. Test samples for each of the WSI configurations were fabricated and tested for electrical continuity. Additional electrical characterization measurements were conducted on two of the test samples. Wafer scale integration, Integrated circuits, Very large scale integration.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 1992
- Accession Number
- ADA248182
Entities
People
- Philip C. Reamy
Organizations
- Air Force Institute of Technology