A Digital Satellite Delay Simulator

Abstract

This document describes the design and operation of a bidirectional digital satellite delay simulator. The data rates which are catered for are 2400, 3600, 7200 and 16000 bps, but other data rates could be included with only minor modification. The circuit is based on the Motorola 6809 microprocessor which uses the Motorola 6852 synchronous serial data adapter (SSDA) as the interface devices.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1991
Accession Number
ADA248386

Entities

People

  • R. W. Ashcroft

Organizations

  • Royal Signals and Radar Establishment

Tags

DTIC Thesaurus Topics

  • Artificial Satellites
  • Classification
  • Data Rate
  • Decoding
  • Foreign Languages
  • Language
  • Microprocessors
  • Power Supplies
  • Satellite Communications
  • Simulators
  • Switches
  • Toggle Switches

Readers

  • Aerospace Test and Evaluation
  • Radio communications and signal processing.
  • Tactical Satellite Communications Systems Engineering.

Technology Areas

  • Space