VLSI for High-Speed Digital Signal Processing
Abstract
We have continued our development of the 12-bit by 11-bit multiplier for our multiprocessor-ring chip. Since the multiplier's performance is the single most important factor in determining the maximum speed at which our system can operate, it is essential that this task be performed in the best possible manner. Our goal was that this multiplier operate in approximately 30 ns, so that our overall chip speed could reach 30 MHz. The multiplier was designed to accommodate eleven-bit data and twelve-bit coefficients. In addition to the above-cited operating speed goal, we needed to make the multiplier small enough that five complete processors, including five multipliers, can be included on a single IC (which employs 2-microns CMOS technology). As mentioned in the previous progress report, after completing the multiplier's layout and verifying its correct functioning via logic simulation, we performed SPICE simulations on the various multiplier critical-path components. These simulations indicated an operating speed well under 30 ns. We next fabricated a MOSIS TinyChip (2.22 mm x 2.25 mm, in 2-micron technology) with this 12-bit by 11-bit multiplier and a small block of coefficient RAM as well as a small dual- port register block. this allowed us to test the multiplier's performance in an environment that closely simulated the five-processor-ring system.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 31, 1992
- Accession Number
- ADA250365
Entities
People
- Alan N. Willson Jr.
Organizations
- University of California, Los Angeles