Branch Recovery with Compiler-Assisted Multiple Instruction Retry

Abstract

In processing systems where rapid recovery from transient faults is important, schemes for multiple instruction rollback recovery may be appropriate. Multiple instruction retry has been implemented in hardware by researchers and also in mainframe computers. This paper extends compiler-assisted instruction retry to a broad class of code execution failures 1. Five benchmarks were used to measure the performance penalty of hazard resolution. Results indicate that the enhanced pure software approach can produce performance penalties consistent with existing hardware techniques. A combined compiler/hardware resolution strategy is also described and evaluated. Experimental results indicate a lower performance penalty than with either a totally hardware or totally software approach.

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Document Details

Document Type
Technical Report
Publication Date
Jul 10, 1992
Accession Number
ADA251920

Entities

People

  • C. C. Li
  • N. J. Alewine
  • S. K. Chen
  • W. Kent Fuchs
  • W. M. Hwu

Organizations

  • University of Illinois Urbana–Champaign

Tags

Communities of Interest

  • Engineered Resilient Systems
  • Materials and Manufacturing Processes
  • Space

DTIC Thesaurus Topics

  • Algorithms
  • Compilers
  • Computer Programming
  • Computer Programs
  • Computers
  • Detection
  • Fault Tolerant Computing
  • Illinois
  • Instructions
  • Mainframe Computers
  • Military Research
  • Recovery
  • Splitting

Fields of Study

  • Computer science

Readers

  • Parallel and Distributed Computing.