VLSI Design for Reliability
Abstract
This report describes the work accomplished during the period Jan 89 to Jan 90 on reliability analysis of VLSI CMOS circuits for electromigration prevention. The work involved three subtasks: (1) development of probabilistic simulation techniques to replace expensive exhaustive circuit simulation, (2) extraction and modeling of transistor circuit description and parasitics from layout, and (3) extraction of metal bus and line models from layout, and calculation of the current densities. In probabilistic simulation, new techniques for computing expected and variance current and voltage waveforms in CMOS circuits are developed and implemented in the program CREST. A proof that electromigration median-time-to-failure predictions are mathematically related to expected and variance current density waveforms in the busses is also given. For very large designs, transistor level probabilistic simulation, although significantly faster than exhaustive deterministic circuit simulation, is still not cost-effective. Thus the development of probabilistic macromodeling simulation techniques is initiated. Initial results show that such an approach is feasible. This will make it possible to include to include other technologies, such as BiCMOS.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 01, 1991
- Accession Number
- ADA253207
Entities
People
- Farid N. Najm
- Hungse Cha
- Ibrahim N. Hajj
- Ping Yang
- Richard Burch
- Russell Limura
- Vasant B. Rao
Organizations
- University of Illinois Urbana–Champaign