Design of a Digital Data Recording System (DRS),

Abstract

The Data Recording System (DRS) for the Delayed Digital Side Lobe Canceler (DDSLC) radar signal processor is a 4 MByte digital data recorder capable of a 10.67 Mword/s data rate (1 word = 32 bits). The recorder may be employed to collect live digitized radar data and store it on high volume data devices such as a Bernoulli cartridge or an optical disk to make it available for future off-line processing. This paper describes the hardware design, controlling software, and implementation of the data recording system developed at NRL. Radar, Data recording.

Document Details

Document Type
Technical Report
Publication Date
Aug 21, 1992
Accession Number
ADA255088

Entities

People

  • Greory C. Tavik
  • James J. Alter

Organizations

  • United States Naval Research Laboratory

Tags

DTIC Thesaurus Topics

  • Data Rate
  • Digital Data
  • Recording Systems

Readers

  • Computer Science/Computer Engineering/Data Science/Digital Signal Processing.
  • Database Systems and Applications
  • Phased Array Antenna Design.