Temperature Distribution and Thermally Induced Stresses in Electronic Packages

Abstract

This investigation is concerned with the steady state temperature and thermally induced stress distributions in electronic packages due to heat generated by the chip. Finite Element codes were employed to solve for the distribution of temperature and stresses within the package. Four parametric studies were undertaken to determine their effects on system behavior. The material study considered two chip and two solder materials and four substrate materials. Convective heat transfer was varied from 200 W/M2 deg C through 500 W/M2 deg C. In the geometric study, chip height to overall height was varied. The effect of package encapsulation was studied. Results are presented for both temperature and stress distributions at the solder interfaces. Thermoelastic stresses, Tri-material package.

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Document Details

Document Type
Technical Report
Publication Date
Sep 01, 1992
Accession Number
ADA257334

Entities

People

  • Andrei Sapsai Jr.

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Coatings
  • Differential Equations
  • Energy
  • Engineering
  • Geometry
  • Heat Flux
  • Heat Transfer
  • Heat Transfer Coefficients
  • Materials
  • Mechanical Engineering
  • Mechanical Properties
  • Mechanics
  • Modulus Of Elasticity
  • Shear Stresses
  • Temperature Gradients
  • Thermal Conductivity
  • Thermal Expansion

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.
  • Structural Dynamics.
  • Thermal Physics or Thermal Science.

Technology Areas

  • Microelectronics
  • Microelectronics - Microelectromechanical Systems