An MCM/Chip Concurrent Engineering Validation.
Abstract
A software link was established between three commercially available Multi-Chip Module design systems: Allegro, EDGE and Finesse. The link was implemented through a database system based on the ROSE system developed under the sponsorship of the DICE program. The code was written in C++ and uses various methods to feed the information in and obtain It out of the design systems: IGES for Allegro, SKILL for EDGE and d-file for Finesse. The DDR2 (Digital Drop Receiver, version 2) multi-chip module from Harris has been entered into the system and routed, and the Information transferred to all the designers through the ROSE database. Concurrent Engineering, Multi-Chip Module, Computer-Aided Design.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 30, 1992
- Accession Number
- ADA257415
Entities
People
- Hector Moreno