Scan-Based Switching Tests

Abstract

This report describes an algorithm for generating scan-based switching tests. The only design consideration required by this algorithm, besides the scan design is the capability to execute two functional clocks with a desired interval between logic scans. The algorithm generates a test vector which is scanned in to cause the source register of the delay path to toggle on the first clock, and captures a transition at the output register of the delay path on the second clock. The algorithm also identifies paths that are not testable, and identifies the points of conflict.

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Document Details

Document Type
Technical Report
Publication Date
Jul 01, 1992
Accession Number
ADA257712

Entities

People

  • Larry D. Bashaw
  • Ted H. Vriezen

Organizations

  • Harris Corporation

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Air Force
  • Algorithms
  • Application-Specific Integrated Circuits
  • Circuits
  • Clocks
  • Demographic Cohorts
  • Demonstrations
  • Fabrication
  • Identification
  • Integrated Circuits
  • Intervals
  • Logic
  • Logic Elements
  • Logic Gates
  • Nand Gates
  • Semiconductor Manufacturing
  • Test And Evaluation

Fields of Study

  • Computer science

Readers

  • Computer Programming and Software Development.
  • Image Processing and Computer Vision.
  • Integrated Circuit Design and Technology.