Parallel Simulation of Structural VHDL Circuits on Intel Hypercubes

Abstract

Many VLSI circuit designs are too large to be simulated with VHDL in a reasonable amount of time. One approach to reducing the simulation time is to distribute the simulation over several processors. This research creates an environment for designing and simulating structural VHDL circuits on the Intel iPSC/2 and iPSC/860 Hypercubes. Logic gates and system behaviors are partitioned among the processors, and signed changes are shared via event messages. Circuit simulations are run over the SPECTRUM parallel simulation testbed, and the null- message paradigm is used to avoid deadlock. Structural circuits ranging from forty to over one thousand logic gates are correctly simulated. Although no attempt is made to find optimal partitioning strategies, speedups are obtained for some configurations.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1992
Accession Number
ADA258999

Entities

People

  • Thomas A. Breeden

Organizations

  • Air Force Institute of Technology

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Abstracts
  • C Programming Language
  • Circuits
  • Computer Programming
  • Computer Programs
  • Computers
  • Digital Circuits
  • Electronic Circuits
  • Language
  • Logic
  • Logic Gates
  • Nand Gates
  • Operating Systems
  • Parallel Processing
  • Plastic Explosives
  • Shell Scripts
  • Simulations

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.