A Parallel Crossbar Routing Chip for a Shared Memory Multiprocessor
Abstract
This thesis describes the design and implementation of an integrated circuit and associated packaging to be used as the building block for the data routing network of a large scale shared memory multiprocessor system. A general purpose multiprocessor depends on high-bandwidth, low-latency communications between computing elements. This thesis describes the design and construction of RN1, a novel self-routing, enhanced crossbar switch as a CMOS VLSI chip. This chip provides the basic building block for a scalable pipelined routing network with byte-wide data channels. A series of RN1 chips can be cascaded with no additional internal network components to form a multistage fault-tolerant routing switch. The chip is designed to operate at clock frequencies up to 100Mhz using Hewlett-Packard's HP34 1.2 micron process. This aggressive performance goal demands that special attention be paid to optimization of the logic architecture and circuit design.... Parallel processing, Computer architecture, Multistage routing network.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 1991
- Accession Number
- ADA259489
Entities
People
- Henry Minsky
Organizations
- Massachusetts Institute of Technology