Multiple-Valued Programmable Logic Array Minimization by Concurrent Multiple and Mixed Simulated Annealing

Abstract

The process of finding a guaranteed minimal solution for a multiple- valued programmable logic expression requires an exhaustive search. Exhaustive search is not very realistic because of enormous computation time required to reach a solution. One of the heuristics to reduce this computation time and provide a near-minimal solution is simulated annealing. This thesis analyzes the use of loosely-coupled, course-grained parallel systems for simulated annealing. This approach involves the use of multiple processors where interprocess communication occurs only at the beginning and end of the process. In this study, the relationship between the quality of solution, measured by the number of products and computation time, and simulated annealing parameters are investigated. A simulated annealing experiment is also investigated where two types of moves are mixed. These approaches provide improvement in both the number of product terms and computation time.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1992
Accession Number
ADA260379

Entities

People

  • Cem Yildirim

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algorithms
  • Charge Coupled Devices
  • Computations
  • Computer Science
  • Computers
  • Electrical Engineering
  • Engineering
  • Military Research
  • Multithreading
  • Parallel Computing
  • Parallel Processing
  • Probability
  • Random Walk
  • Schools
  • Theses
  • United States
  • Very Large Scale Integration

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Computational Modeling and Simulation
  • Parallel and Distributed Computing.