VLSI for High-Speed Digital Signal Processing
Abstract
During the past quarter we have fabricated and tested a 12-bit by 16- bit multiplier based on our previous multiplier architecture but using third order recoding. That is, we use an 8-to-1 multiplexer selected by 3 input bits to form each partial products instead of the 4-to-1 multiplexer selected by 2 input bits as used previously. The partial products (1X, 3X, 5X, and 7X the coefficient value) are stored in an on-chip RAM. Fig. 1 shows the architecture of the test.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 31, 1992
- Accession Number
- ADA260754
Entities
People
- Alan N. Willson Jr.
Organizations
- University of California, Los Angeles