Utilization of an Electronic Circuit Simulator in CMOS Latch-Up Studies

Abstract

The 2-D device simulator presented in this work allows the investigation of the effect of ionizing radiation dose rate on the performance of CMOS circuits. The simulator is composed of two parts, a diffusion current module and a lumped-element module. The first module solves the current transport equations with the aid of the HSPICE code. The lumped-element module then simulates the electrical characteristics of the parasitic pnpn structure (present in CMOS circuits) using the results from the first module as input parameters. The model was applied to study the latch-up vulnerability of a CMOS inverter as a function of circuit layout and distribution of substrate contacts. Results of radiation hardening efforts are presented.

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1992
Accession Number
ADA260787

Entities

People

  • L. Varga

Organizations

  • Defence Research and Development Canada

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Bipolar Junction Transistors
  • Boltzmann Equation
  • Computational Fluid Dynamics
  • Differential Equations
  • Dose Rate
  • Electronic Circuits
  • Equations
  • Ionizing Radiation
  • Pnp Transistors
  • Radiation Effects
  • Radiation Hardening
  • Semiconductors
  • Simulations
  • Simulators
  • Three Dimensional
  • Two Dimensional
  • Very Large Scale Integration

Fields of Study

  • Engineering
  • Physics

Readers

  • Computational Modeling and Simulation
  • Integrated Circuit Design and Technology.
  • Nuclear and Radiation Engineering.

Technology Areas

  • Microelectronics