Construction of a Connectionist Network Supercomputer
Abstract
The first finding is that, in the assessment of our reviewers, the project is technically sound. In particular, there was general agreement that the motivations are reasonable, the physical packaging scheme is plausible, the processor interconnection network is satisfactory, and the VLSI task is attainable. The software strategy was only briefly presented; a more complete software review is planned at a later time. There were several minor points made by the reviewers which are being incorporated in the CNS-1 Architecture Specification. However, we also received suggestion for making better use of industry and academic 'standards', thereby allowing more widespread use of the CNS-1 by other in the field. The subsequent consideration of these suggestion led to the second major result of the review. We are adopting an industry standard instruction set architecture (ISA) for the scalar processor within the Torrent VLSI chip. Although this decision directly only affects about 15% of the silicon die area (making it slightly more complex to design), the repercussions are extensive in the software area. By using a standard ISA (we have selected the MIPS R3000), system software, tools and application libraries. In addition, machines executing the R3000 instruction set are widely available and will be used as development platforms throughout the life of CNS-1. The basic architecture of the Torrent chip remains the same; it is a scalar processor with a SIMD array of moderate precision datapaths for neural computation. The SIMD array now interfaces to the scalar processor as a vector coprocessor.
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 01, 1993
- Accession Number
- ADA260929
Entities
Organizations
- University of California, Berkeley