Chip-Level Testability Requirements Guidelines
Abstract
This report provides guidelines and rationale that will assist system developers in specifying consistent, necessary, and achievable chip-level testability requirements. A bottom-up design procedure is recommended that emphasizes the importance of chip testability estimation and built-in-test evaluation during chip design to minimize system life-cycle cost. A comprehensive set of cost-related testability attributes was developed, which address test generation, test application, and fault isolation and repair. This set of attributes was then prioritized on the basis of usefulness and estimation cost. A set of chip-level design-for-testability and built-in-test techniques were selected from open literature sources. Preliminary analyses of eleven of the more promising techniques considered nine criteria in the areas of: impact on testability, cost, and applicability to standard design practices. Three of the techniques were subjected to in-depth analyses that included the results of case studies. The techniques considered in the in-depth studies were: Circular Built-In-Self-Test, LSSD On-Chip Self-Test (LOCST), and CrossCheck.... Testability, Design-for-testability, Built-in-test, Fault coverage, Reliability, Availability, Life-cycle cost.
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 01, 1992
- Accession Number
- ADA262583
Entities
People
- James W. Watterson
- Mark Royals
- Nick Kanopoulos
Organizations
- RTI International