An MCM/Chip Concurrent Engineering Validation
Abstract
We report on the MOST software system, which implements a concurrent physical design environment for Multi-Chip Modules. The system integrates the work of design teams distributed across a network and using different CAD systems. At present the following systems have been integrated: Cadence's Edge 2.1, Cadence's Allegro 6.1, AutoDesk's AutoCad 12.0, and Harris' Finesse. Software linka were established allowing data from those systems to be shared through a ROSE (Rensselaer Object Storage Environment) database management developed under the sponsorship of the DICE program. The code was written in C++ and uses various methods to feed the information in and obtain it out of the design systems: IGES for Allegro, SKILL for Edge and dfile for Finesse, while the AutoCad link is a direct one. The DDR2 (Digital Drop Receiver, version 2) multi-chip module from Harris was entered into the system and routed utilizing a redundant route scheme. The exercise used a concurrent approach, the data defining parts and placement entered through Finesse, the parts modified in Edge, the route done in Allegro and the final merge and verification performed with the Edge tool.... Concurrent engineering, Multi-chip module, Computer-aided design, CAD System integration.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 31, 1992
- Accession Number
- ADA262959
Entities
People
- Hector Moreno
- Shuane Stark