Low Latency Messages on Distributed Memory Multiprocessors
Abstract
This paper describes many of the issues in developing an efficient interface for communication on distributed memory machines and proposes a portable interface. Although the hardware component of message latency is less than one microsecond on many distributed memory machines, the software latency associated with sending and receiving typed messages is on the order of 50 microseconds. The reason for this imbalance is that the software interface does not match the hardware. By changing the interface to match the hardware more closely, applications with fine grained communication can be put on these machines. Based on several tests that we have run on the iPSC/860, we propose an interface that will better match current distributed memory machines. The model used in the proposed interface consists of a computation processor and a communication processor on each node. Communication between these processors and other nodes in the system is done through a buffered network. Information that is transmitted is either data or procedures to be executed on the remote processor. The dual processor system is better suited for efficiently handling asynchronous communications compared to a single processor system. The ability to send data or procedure invocations is very flexible for minimizing message latency, based on the type of communication being performed. This paper describes the tests performed and the proposed interface.... Parallel computers, Distributed memory, Communication, Message latency.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 1993
- Accession Number
- ADA268985
Entities
People
- Joel Saltz
- Matthew Rosing