Decoupled Computer Architectures for Very High-Speed Technologies

Abstract

The long-term goal of this project is to develop the capability to apply and effectively use emerging high-speed IC technologies such as gallium- arsenide. Success in this endeavor requires experience with circuits, packaging, and architecture, not only in the new technologies, but also in current MOS IC technologies. The fundamental problem addressed here is that though GaAs systems can now (or soon) quite readily be built with 100-150 MHz clock rates, the scaling beyond that speed is greatly complicated due to two effects: (1) some subsystems within a computer can support faster clock rates without much special consideration, but there are subsystems (most notably memory and communications) that cannot readily be made to follow the faster clock rates; and (2) conventional computer architecture is not capable of effectively dealing with high latency operations. As clock rates for some (but not all) of the subsystems of a computer increase, the relative latency of the remaining subsystems grows.

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 1993
Accession Number
ADA271646

Entities

People

  • Stephen I. Long
  • Steven E. Butner

Organizations

  • University of California, Santa Barbara

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Computer Architecture
  • Computer Programming
  • Computer Programs
  • Computers
  • Debugging
  • Digital Circuits
  • Fabrication
  • Field Effect Transistors
  • Instruction Set Architecture
  • Integrated Circuits
  • Inverters
  • Logic Gates
  • Materials Engineering
  • Operating Systems
  • Semiconductors
  • Three Dimensional
  • Transmission Lines

Readers

  • Economics
  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.

Technology Areas

  • Microelectronics