The Effects of Block Size on the Performance of Coherent Caches in Shared-Memory Multiprocessors
Abstract
Several studies have shown that the performance of coherent caches depends on the relationship between the cache block size and the granularity of sharing and locality exhibited by the program. Large cache blocks exploit processor and spatial locality, but may cause unnecessary cache invalidations due to false sharing. Small cache blocks can reduce the number of cache invalidation, but increase the number of bus or network transactions required to load data into the cache. In this dissertation we use reference traces from a variety of parallel programs and detailed simulation of a scalable shared-memory multiprocessor to examine the effects of cache block size on the performance of coherent caches and quantify this impact with respect to the network bandwidth and latency. Our results suggest that, regardless of the available bandwidth or latency, applications with good spatial locality favor long cache lines, and for these applications the relative benefits of longer cache lines increase with the bandwidth and latency.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 01, 1993
- Accession Number
- ADA272838
Entities
People
- Cezary Dubnicki
Organizations
- University of Rochester