Virtual Memory Management and Virtual Bus Overloading on Multiple Channel Architectures

Abstract

Today's computational environment requires the processing capabilities available only through parallel architectures. The bottleneck that limits the potential of parallel processing is communication between processors, memories, and other hardware devices. A proposed multiple channel architecture (MCA) utilizes tunable semiconductor lasers and fiber optic cables that serve as the communication medium between processor, memory, and I/O nodes. A memory management unit (MMU) was completely described and implemented in a multiprocessor simulator. A permutation-based interleaving (PBI) scheme was utilized to reduce the chance of memory access collisions. Virtual bus utilization, number of collisions, and message traffic patterns were studied under various amounts of overloading. Results show that it is possible to maintain processor efficiency while reducing demand for channel availability.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1993
Accession Number
ADA274127

Entities

People

  • John N. Armitstead

Organizations

  • Air Force Institute of Technology

Tags

Communities of Interest

  • Materials and Manufacturing Processes
  • Space

DTIC Thesaurus Topics

  • Air Force
  • Algorithms
  • Artificial Intelligence
  • Collisions
  • Communication Channels
  • Computations
  • Computer Programs
  • Computers
  • Environment
  • Lasers
  • Operating Systems
  • Parallel Computing
  • Parallel Processing
  • Permutations
  • Simulations
  • Simulators
  • Standards

Fields of Study

  • Computer science
  • Engineering

Readers

  • Parallel and Distributed Computing.
  • Radio communications and signal processing.

Technology Areas

  • Directed Energy
  • Microelectronics