Design and Evaluation of Fault Tolerance in Opto-electronic Computing
Abstract
The first area of research is Data-Flow Clustering. In synchronous circuits (described in terms of registers and combinational nodes) it is known that the feedback loops are dominant in determining the achievable clock period for the circuit. More precisely, the maximum delay to register ratio over all loops in the circuit (called the iteration bound) is a lower bound on the clock period. Furthermore, if the combinational nodes are fine-grained in nature, the iteration bound very closely reflects the achievable clock period through retiming. However, because of size constraints it is often necessary to partition such a circuit into multiple modules (for example FPGA's). The second area of research is network partitioning. We study the classical problem of finding the Minimum-Cut in an undirected graph, given source and sink nodes, s and t. We reformulate the problem as a continuous placement problem. We show the correspondence between the Min-Cut problem and the placement problem which is then solved iteratively using gradient methods. In addition, this method has good potential for efficient parallel implementation. We provide experimental data on the effectiveness of our approach.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 03, 1993
- Accession Number
- ADA274281
Entities
People
- Ting-ting Y. Lin
Organizations
- University of California, San Diego