Partitioning Structural VHDL Circuits for Parallel Execution on Hypercubes

Abstract

Distributing simulations among multiple processors is one approach to reducing VHDL simulation time for large VLSI circuit designs. However, parallel simulation introduces the problem of how to partition the logic gates and system behaviors among the available processors in order to obtain maximum speedup. This research investigates deliberate partitioning algorithms that account for the complex inter-dependency structure of the circuit behaviors. Once an initial partition has been obtained, a border annealing algorithm is used to iteratively improve the partition. In addition, methods of measuring the cost of a partition and relating it to the resulting simulation performance are investigated. Structural circuits ranging from one thousand to over four thousand behaviors are simulated. The deliberate partitions consistently provided superior speedup to a random distribution of the circuit behaviors.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1993
Accession Number
ADA274390

Entities

People

  • Kevin L. Kapp

Organizations

  • Air Force Institute of Technology

Tags

Communities of Interest

  • C4I
  • Energy and Power Technologies
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algorithms
  • Application Software
  • Circuit Analysis
  • Circuits
  • Computer Programming
  • Computer Programs
  • Computers
  • Content Addressable Memory
  • High Level Languages
  • Language
  • Logic
  • Logic Gates
  • Operating Systems
  • Programming Languages
  • Simulators
  • Standards
  • Two Dimensional

Readers

  • Computational Modeling and Simulation
  • Operations Research
  • Parallel and Distributed Computing.