Real-Time Data Filtering and Compression in Wide Area Simulation Networks
Abstract
We present a new memory based CODEC architecture to design a special purpose hardware for real-time multibit compression/decompression of binary data. The proposed architecture is based on a novel idea of mapping the decoding/encoding tree of any variable length binary code on to a memory device that corresponds to simultaneous decoding/encoding of multiple bits. The hardware is programmable, easily adaptable and yields a high compression rate. A prototype 2-micron VLSI chip based on this architectural idea has been designed. This chip occupies a silicon area of 6.9 x 6.8 square millimeters and it contains 49,695 transistors with estimated compression rate of 88 Mbits/sec and a decompression rate of 53 Mbits/sec with a clock rate of 50 MHz. The algorithms have been tested with different types of variable-length binary codes including the JPEG baseline compression scheme. CODEC, Compression, Decompression, JPEG, Multibit data compression/decompression, Tree based code, Reverse code, Reverse binary tree, Memory map, Perfect map, Contiguous binary superstring, CBS.
Document Details
- Document Type
- Technical Report
- Publication Date
- Oct 02, 1992
- Accession Number
- ADA275108
Entities
People
- Arunabh Mukherjee
- M. Bassiouni
Organizations
- University of Central Florida