Design and Packaging of Fault Tolerant Optoelectronic Multiprocessor Computing System
Abstract
There is considerable interest in developing optical interconnects for multi-chip modules (MCM). As a consequence, there is the basic need in developing a methodology for partitioning the system for effective utilization of the optical and electronic technologies. For the given netlist of a system design, key question to be answered is where to use optical interconnections. This paper introduces the Computer Aided Design (CAD) approach for partitioning opto-electronic systems into Opto-Electronic Multichip Modules (OE MCM). We will first discuss the design tradeoff issues in optoelectronic system design including speed, power dissipation, area and diffraction limits for free space optics. We will then define a formulation for OE MCM partitioning and describe new algorithms for optimizing this partitioning based on the minimization of the power dissipation. The models for the algorithms are discussed in detail and an example of a multistage interconnect network is given. Different results, with the number and size of chips being variable, are presented where improvement for the system packaging has been observed when the partitioning algorithm are applied.
Document Details
- Document Type
- Technical Report
- Publication Date
- Dec 14, 1993
- Accession Number
- ADA275896
Entities
People
- Sing H. Lee
Organizations
- University of California, San Diego