Proof of Concept for the Rewrite Rule Machine: Interensemble Studies
Abstract
The main goal was to learn through simulation about the functionality and performance on realistic applications of an RRM system consisting of a collection of RRM ensemble chips (each such chip being a SIMD processor) connected on a network, and to design mechanisms to support the simultaneous parallel computation of applications across many such ensemble chips. To achieve these goals we first built a high-level interensemble simulator and ran a collection of benchmarks on it under varying assumptions about several architectural parameters to obtain a first estimate of the communication requirements for the RRM and to determine the feasibility of those requirements in view of existing network technology. Using a second, very detailed register- transfer level simulator of a single ensemble and the performance results of a collection of applications run on it, together with modeling above the ensemble level, we also estimated interensemble performance; in this way we were able to obtain more detailed and accurate interensemble performance estimates. Mechanisms supporting parallel computations across many ensembles were also studied and designed
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 23, 1994
- Accession Number
- ADA276506
Entities
People
- José Meseguer
Organizations
- SRI International