An Analog Preprocessing Architecture for High-Speed Analog-to-Digital Conversion

Abstract

This thesis investigates the feasibility of implementing an analog- to-digital converter (ADC) based on a new symmetrical number system (SNS). This preprocessing architecture decomposes the analog amplitude analyzing function of an ADC into a number of sub-operations (moduli). Each sub-operation folds the analog signal with a folding period proportional to the value of the modulus. Through the use of the SNS encoding and recombining the results of the sub- operations, a definitive performance enhancement is achieved. The number of comparators required is reduced considerably, allowing more bandwidth to be used in the folding circuits. The overall design effort demonstrates a 9-bit design with a total of 23 comparators. SPICE simulations are developed and the performance demonstrated. Also identified are the areas in which further research is required. Analog-to-Digital converter, Symmetrical number system , Analog preprocessing for analog-to-digital conversion.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1993
Accession Number
ADA276737

Entities

People

  • Jorge A. Esparza

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Energy and Power Technologies
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Amplifiers
  • Circuits
  • Clocks
  • Converters
  • Diagrams
  • Digital Circuits
  • Dynamic Range
  • Electrical Engineering
  • Energy Consumption
  • Engineering
  • Frequency
  • Frequency Response
  • Power Supplies
  • Simulations
  • Standards
  • United States
  • United States Naval Academy

Fields of Study

  • Physics

Readers

  • Approximation Theory.
  • Integrated Circuit Design and Technology.
  • Systems Analysis and Design