Investigation of Modularly Configured Attached Processors with Intelligent Memories

Abstract

A new architecture for high-performance parallel attached processors is described in this paper. Based on this architecture, an attached processor can be implemented as multiple memory-to-memory pipelines, each being constructed with a class of fundamental components. The unique features are that the attached processor can be configured to match a set of algorithms and its memory controllers can be programmed to fit the access patterns required by the algorithms. As a result, high utilization of the processing logic for given sets of algorithms can be obtained. An example based on matrix multiplication is used for illustration. Finally, design issues related to the implementation of the attached processor based on an MCM technology are discussed. Attached processor, Interconnected pipeline, Memory-to-memory pipeline, Sustained execution rate, Multichip module.

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Document Details

Document Type
Technical Report
Publication Date
Mar 31, 1994
Accession Number
ADA278418

Entities

People

  • Glenn Gibson
  • Sanjay Singh
  • Vijay P Singh
  • Yi-chieh Chang
  • Yu-cheng Liu

Organizations

  • University of Texas at El Paso

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies
  • Human Systems

DTIC Thesaurus Topics

  • Arithmetic
  • Binary Arithmetic
  • Comparators
  • Complementary Metal-Oxide Semiconductors
  • Computers
  • Data Transmission
  • Dissipation
  • Efficiency
  • Electrical Engineering
  • Host Computers
  • Multichip Modules
  • Operating Systems
  • Parallel Computing
  • Parallel Processing
  • Semiconductors
  • Simulators
  • Standards

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.