Rapid and Accurate Timing Simulation of Radiation-Hardened Digital Microelectronics Using VHDL
Abstract
This dissertation presents the development of a fast, accurate, timing simulation capability based on VHSIC Hardware Description Language (VHDL) without the use of back annotation of timing delay information. This VHDL-based timing simulator is intended for use with radiation-hardened microelectronics in simulating timing of circuit operation in pre-radiation, post-radiation (1 Mrad(Si) total dose), and ionizing dose radiation environments. Development of the timing models are presented. The implementation of the timing models are incorporated into a VHDL library composed of basic logic gates and flip-flops. Simulations of complex circuits were run in SPICE and VHDL to assess the timing accuracy and simulation run time of the VHDL-based timing simulator versus SPICE. Results of the simulations are presented. Final evaluation of the simulator included testing of a microprocessor control unit. In all cases, the VHDL-based simulation ran over two orders of magnitude faster than the equivalent SPICE simulation. In the pre- and post-radiation environment, accuracy estimates are usually within five percent and never exceed 12 percent. Worst-case timing estimate errors increase above 15 percent for dose rates above 1.Ox1O(exp 11) rads(Si) per second. This VHDL-based timing simulator represents an improvement over SPICE in the ability to quickly simulate complex circuits. CMOS Logic simulation, Logic circuit simulation, Radiation-hardened microelectronics, Transient radiation effects, VHDL.
Document Details
- Document Type
- Technical Report
- Publication Date
- Mar 01, 1994
- Accession Number
- ADA278644
Entities
People
- Charles P. Brothers Jr.
Organizations
- Air Force Institute of Technology